1. Field of the Invention
The present invention generally relates to image sensors. More particularly, the present invention relates to active pixel sensors in which the read-out circuitry thereof is shared by two or more sensor elements.
A claim of priority is made to Korean patent application nos. 2005-61968 and 2005-68103, filed Jul. 9, 2005, and Jul. 26, 2005, respectively, the contents of which are incorporated by reference herein in their entireties.
2. Description of the Related Art
Certain types of image sensors utilize photo detectors to capture incident light and convert the light to an electric charge capable of image processing. Examples include Complimentary Metal Oxide Semiconductor (CMOS) image sensors (CIS). CIS devices are generally characterized by analog sensing circuits coupled to CMOS control circuits. The analog sensing circuits include an array of photo detectors having access devices (e.g., transistors) for connection to word lines and bit lines. The CMOS control circuits may include a timing generator and a variety of image processing circuits, such as row decoders, column decoders, column amplifiers, output amplifiers, and so on. Generally speaking, the configuration of the CIS device is analogous to that of a CMOS memory device.
FIG. 1 is a block diagram of an example of a CMOS image sensor (CIS). The CMOS image sensor of FIG. 1 generally includes an active pixel sensor (APS) array 10, a timing generator 20, a row decoder 30, a row driver 40, a correlated double sampling and digital converting (CDS) circuit 50, an analog to digital converter (ADC) 60, a latch circuit 70, and a column decoder 80.
Those of ordinary skill are well-acquainted with the operation of the CIS represented in FIG. 1, and a detailed description thereof is therefore omitted here. Generally, however, the timing generator 20 controls the operational timing of the row decoder 30 and column decoder 80. The row driver 40 is responsive to the row decoder 30 to selectively activate rows of the active pixel array 10. The CDS 50 and ADC 60 are responsive to the column decoder 80 and latch circuit 70 to sample and output column voltages of the active pixel array 10. In this example, image data is output from the latch circuit 70.
The APS array 10 contains a plurality of active unit pixels arranged in rows and columns. Each active unit pixel includes a photoelectric conversion device and readout circuitry for transferring charges of the photoelectric conversion device to an output line.
Reference is now made to FIG. 2 which is an equivalent circuit diagram of an example of an active pixel 22 of the APS array 10 shown in FIG.
A photoelectric conversion element PD (e.g., a photo-diode, a photo-gate type image element, etc.) of the active pixel 22 captures incident light and converts the captured light into an electric charge. The electric charge is selectively transferred from the photoelectric conversion element PD to a floating diffusion region FD via a transfer transistor TX. The transfer transistor TX is controlled by a transfer gate TG signal. The floating diffusion region FD is connected to the gate of a drive transistor Dx which functions as a source follower (amplifier) for buffering an output voltage. The output voltage is selectively transferred as an output voltage OUT by a select transistor Sx. The select transistor Sx is controlled by a row select signal SEL applied to the gate of the select transistor Sx. Finally, a reset transistor Rx is controlled by a reset signal RS to selectively reset charges accumulated in the floating diffusion region FD to a reference voltage level.
It is noted that one or more of the transistors shown in FIG. 2 may be optionally omitted. For example, the floating diffusion region FD may be electrically connected to the photoelectric conversion element PD, in which case the transfer transistor TX may be omitted. As another example, the drive transistor Dx may be electrically connected to the output line OUT, in which case the selection transistor Sx may be omitted.
In an effort to increase pixel density, it is known to configure CIS devices such that the unit active pixels thereof each contain multiple photoelectric conversion elements PD which share common readout circuitry. However, conventional shared pixel CIS configurations and layouts suffer drawbacks in that the photoelectric conversion elements PD are defined by relatively small light photoelectric conversion areas. In addition, the photoelectric conversion areas are separated from one another at unequal pitches in row and/or column directions. Thus, the conversion efficiency and/or image quality of these CIS devices adversely impacted.